The escalating demands for high density and performance associated with non-volatile memory devices require small design features, high reliability and increased manufacturing throughput. The reduction of design features, however, challenges the limitations of conventional methodology.
For example, when fabricating memory devices with small design features, it is difficult to maintain a relatively thick or vertically tall photoresist with smaller and smaller pitches. The top of the photoresist starts to round. This may result in a poor junction profile associated with subsequent ion implantation.